| Summary |
| ECS SF2 motherboard information. |
| Form Factor |
- Form Factor: microATX
- Size: 244*230mm
- Layer: 4 layers
- Rear I/O Panel: ECS Rear I/O panel
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| CPU Support |
- Type: 1.5G/1.6G/1.7G…2.8G and above
- Socket type: P4 Socket478
- FSB Speed: 400/533/800MHz 1.3.
- Chipsets North Bridge: SiS661FX South Bridge: SiS964 / 964L LPC
- Super I/O: ITE8705F AC’97
- Audio Codec: ALC655
- LAN: RTL8100C IEEE1394: VT6307
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| System Memory |
- Module Speed: DDR266 / DDR333/ DDR400
- Socket Type: Two DDR 184-pin unbuffered DIMM sockets
- Maximum Memory size: 2GB.
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| Core Logic (Chipset) |
SF2 Internal Specification Ver 1.1 4
- North Bridge: SiS661FX Host interface controller.
- Intel® Pentium® 4 processor family with data transfer rate
- Hyper-Threading Technology
- 12 outstanding transactions and out-of-order completion
- Quasi-synchronous/as ynchronous Host-to-DRAM timing AGTL+ & AGTL compliant bus driver with auto compensation DRAM controller
- DDR400/DDR333/DDR266 SDRAM Supports up to 2 un-buffered DIMM DDR400 Up to 1 GB per DIMM with maximum memory size
- 32Mb, 64Mb, 128Mb, 256Mb, 512Mb, 1Gb SDRAM technology with page size from 2KB up to 32 KB
- DDR SDRAM CAS Latency at options of 2, 2.5, & 3 clocks
- Suspend-To-RAM (STR).
AGP controller
- AGP 3.0 compliant.
- 1.5V AGP Interface
- Graphic Window Size from 4Mbytes to 512Mbytes
- Pipelined process in CPU-to-AGP Access
- AGP 8X/4X Interface w/ Fast Write Transaction High Throughput
- SiS MuTIOL® 1G interconnecting to SiS964 MuTIOL® 1G Media I/O Bi-directional 16 bit data bus
- Perform 1GB/s bandwidth in 133MHz x 4 mode
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| IO Controller |
South Bridge: SiS964 / 964L
- Support Hi-Precision Event Timer (HPET) for Microsoft Windows
- Multiple DMA Bus Architecture Concurrent servicing of all DMA Devices: Dual IDE Controllers, SATA controller, USB 1.1 HC, USB 2.0 HC, MAC Controller and Audio/Modem DMA Controller.
- Separate 32 Bit Input and Output Data Bus Scheme for each DMA Device
- Support isochroous request and continuous packet transmission
- Integrated MuTIOL 1G to PCI Bridge PCI 2.3 Specification Compliance Supports up to 6 PCI Masters Each PCI request can be programmed at one of four level priority
- Dual IDE Master/Slave controller
- Integrated Multithreaded I/O Link Mastering with Read Pipelined Streaming Dual Independent IDE Channels Each with 32 DW FIFO
- Supports PIO mode 0,1,2,3,4 and Multiword DMA mode 0,1,2.
- Supports Ultra DMA 33/66/100/133. Serial ATA Host Controller (SiS964L without SATA Host Controller) Two independent ports and flexible channel allocation Compliant with Serial ATA 1.0 Specification Ultra DMA 150
- Support Power saving mode
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| Audio Chipset |
Integrated Audio Controller with AC97 Interface:
- AC'97 v2.2 compliance 6 channels of AC97 speaker outputs and V.90 HSP-Modem
- AC’97 Audio Codec Compliant with AC'97 v2.2 specification
- 18-bit stereo full-duplex CODEC with independent and variable sampling rate
- Advanced power management 48-pin LQFP
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| Video and graphics |
- 32-bit floating point format VLIW triangle setup engine
- 2 pixel rendering pipelines and 4 texture units
- Ultra-AGPIITM up to 2.7GB/s bandwidth
- Up to 166 MHz 3D engine clock speed
- 16/24/32 bits integer Z buffer format and 32 bits floating point Z format
- Supports up to 2048x2048 texture size MPEG-2/1
- Video Decoder MPEG-2 ISO/IEC 13818-2 MP@HL and MPEG-1 ISO/IEC 11172-2 standards compliant
- Advanced hardware DVD acceleration logic
- Up to 20 Mbit/sec bit rate decoding Support VCD, DVD and HDTV (all ATSC modes) decoding Direct DVD to TV playback
- Video Accelerator Supports YUV-to-RGB color space conversion
- Bi-linear video interpolation with integer increments of 1/2048
- RGB555, RGB565, YUV422, and YUV420 video playback format
- Independent Gamma correction RAM Supports Direct Draw Drivers High Integration
- CRT FIFOs to support ultra high resolution graphics modes and reduce CPU wait-state
- Two clock generators for CRT, 2D, 3D and MPEG Engine
- TV Encoder Interface
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| Jumper Settings |
|
Location |
Header Type |
Description |
Function |
|
JP1 |
Header 3*1 |
Clear CMOS |
1-2: Normal
2-3: Clear |
|
JP3 |
Header 3*1 |
BIOS Protection |
1-2: Write Enable
2-3: Write Disable |
|
JP4 |
Header 3*1 |
Reserved |
1-2: Reserved
2-3: Reserved |
|
JP5 |
Header 3*1 |
Reserved |
1-2: Reserved
2-3: Reserved |
|
JPT1 |
Header 3*1 |
COM1 Pin9
Function Selection |
1-2: Ring
2-3: VCC |
|
JPT2 |
Header 3*1 |
COM2 Pin9
Function Selection |
1-2: Ring
2-3: VCC |
|
JPT3 |
Header 3*1 |
Reserved |
1-2: Reserved
2-3: Reserved | |
| Connectors |
- IDE Headers: Two 40-pin IDE low profile headers
- Devices: Up to 4 IDE devices Speed: PIO mode, ATA100/133 1.8. Serial ATA
- Revision: Serial ATA V1.0 Compliant
- Connectors: Two 7-pin SATA connectors
- Devices: Up to 2 SATA devices
- Speed: 1.5Gbps 1.9. Audio Connectors and Headers Real Audio
- Connector: Line Out, Line In, Microphone In
- One CD-in header (4*1)
- One Aux-in header (4*1)
- One Intel® specification audio header (5*2) 1.10.
USB / 1394 connectors and headers
- USB Revision: USB V2.0 Compliant
- Connector: Two rear USB connector with 4-ports in rear I/O panel
- Header: Two Intel specification USB header (5*2) with 4-ports in front I/O 1394
- Speed: 400Mbps
- Connector: One rear connector with 1-port in rear I/O panel
- Header: One Intel specification 1394 header (5*2) with 1-port in front I/O
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| Rear Connectors |
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| Related Support FAQs |
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